1. Field of the Invention
The present invention relates to a DLL circuit, a semiconductor device and a phase delay control method.
2. Description of the Related Art
The operation of a semiconductor device such as a memory circuit, an interface circuit, and a CPU is controlled based on a reference clock signal externally supplied. In recent years, with speed-up of the semiconductor device, it is required that a memory circuit can operate correctly at high speed in about 400 MHz. For example, a synchronous DRAM carries out data output in synchronism with the reference clock signal. Such a synchronous DRAM must operate correctly in synchronism with the rising edge and falling edge of the clock signal with about 2.5-ns period. In other words, this means that it is necessary for the memory circuit to operate at the timing of half period of 1.25 ns.
The operation of the synchronous DRAM is controlled by internal clock signals generated based on the reference clock signal. However, in order to guarantee a correct high-speed operation, it is necessary that the phase of the external clock signal as the reference clock signal and the phase of the internal clock signal are coincident with each other or the phase difference of the external clock signal and the internal clock signal is strictly controlled. For the purpose, a DLL circuit is used.
That is, a variable delay circuit delays the external clock signal and outputs as an internal clock signal from the DLL circuit. The phase of the internal clock signal generated in this way and the phase of the external clock signal are compared by the phase comparing circuit, and a feedback phase control is carried out based on the phase shift quantity and the delay quantity of the variable delay circuit is adjusted. In this way, the phase of the internal clock signal is made coincident with the phase of the external clock signal.
A conventional example of such a DLL circuit is known in Japanese Laid Open Patent Application (JP-A-Heisei 11-127063). The structure of this conventional example is shown in FIG. 1. Also, the operation is shown in FIGS. 2A to 2E. Referring to FIG. 1, the external clock signal is supplied to a variable delay circuit 103 as a signal N1 through an input buffer as shown in FIG. 2A. The variable delay circuit 103 delays the signal N1 based on a delay control signal N8 from a delay control circuit 107 to generate a signal N4 as shown in FIG. 2C. The signal N4 is outputted as the internal clock signal through an output buffer 109. Also, the signal N4 is supplied to a timing synchronizing circuit 101.
Also, the signal N1 is divided by a frequency divider 102 and is supplied to a phase comparing circuit 106 as the signal N2 as shown in FIG. 2D. The signal N2 is also supplied to a timing synchronizing circuit 101. The timing synchronizing circuit 101 outputs the signal N2 as the signal N5 in synchronism with the signal N4 as shown in FIG. 2D.
The signal N5 is supplied to the phase comparing circuit 106 as the signal N7 through an output dummy circuit 104 and an input dummy circuit 105 as shown in FIG. 2E. The phase comparing circuit 106 compares the signal N2 and the signal N7 in phase and outputs a phase difference to a delay control circuit 107. The delay control circuit 107 generates the delay control signal based on the phase difference from the phase comparing circuit 106 and outputs it to the variable delay circuit 103 as a signal N8.
The internal clock signal S4 which has been subjected to phase control in this way is used for the control of the timing at which read data is outputted from the output buffer 109, and is in synchronous with the reference clock signal IN. As above-mentioned, the operation frequency of the memory circuit is increased in recent years and the increase of the consumed power (average operating current) becomes a problem. Generally, in a logic circuit composed of CMOS transistors, the charging current and discharge current flow only when the data is switched, i.e., 0 and 1 of the data is switched. Therefore, it is the output buffer and an input buffer and an output dummy circuit and an input dummy circuit that consume the most of current in the DLL circuit of FIG. 1.
Therefore, in the conventional example shown in FIG. 1, the reference clock signal N1 is divided in frequency into xc2xd by the frequency divider 102, so that the number of times of the phase comparison operation is reduced to xc2xd. Therefore, the number of times of the switching operation of the dummy circuit is suppressed to xc2xd and can reduce power consumption.
The operation of the timing synchronizing circuit 101 will be described with reference to FIG. 1. The timing synchronizing circuit 101 has a flip-flop circuit which inputs the signal N2 obtained by frequency-dividing the signal N1 (FIG. 2B) and the signal N4 (FIG. 2B) obtained by delaying the signal N1. The timing synchronizing circuit 101 generates the signal N5 (FIG. 2D) obtained by synchronizing a frequency-division signal of the signal N1 with the signal N4. FIGS. 2A to 2E show timing charts when the timing synchronizing circuit 101 operates normally.
However, the delay quantity from the variable delay circuit 103 changes in accordance with the phase difference between the signal N1 and the signal N4. Therefore, the timing synchronizing circuit 101 takes synchronization between the signals which have no relation substantively. For this reason, there is caused the state in which the signal N2 changes during a setup hold period of the flip-flop circuit of the timing synchronizing circuit 101, i.e., the state in which the rising edge of the signal N4 and the change point of the signal N2 are approximately coincident with each other. As a result, a meta-stable state is caused in which the output of data 1 and the outputs of data 0 balance so that a middle voltage is outputted. Consequently, an unstable operating state is caused such as delay of the rising timing of the signal N5 and the disappearance of a signal waveform.
The phase difference which causes such an erroneous operation occurs in the process of taking the synchronization of the signal N1 and the signal N4. However, it is generally difficult to design to operate the timing synchronizing circuit 101 stably in the wide frequency range.
In conjunction with the above description, a semiconductor integrated circuit with a phase comparing circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-209857). In the semiconductor integrated circuit of this reference, a first control circuit frequency-divides a first signal into 1/n (n is an integer more than 1) in response to a third signal. A second control circuit frequency-divides a second signal into 1/n in response to the third signal. A phase comparing section compares the output signal of the first control circuit and the output signal of the second control circuit in phase.
Therefore, an object of the present invention is to provide a DLL circuit which can reduce the power consumption.
Another object of the present invention is to provide a DLL circuit which can operate stably even if the frequency of an external clock signal changes.
Still another object of the present invention is to provide a DLL circuit which can control the number of times of phase comparison.
Yet still another object of the present invention is to provide a DLL circuit which detects the phase of an input clock signal with respect to a delay signal and can guarantee a stable operation.
Also, another object of the present invention to provide a DLL circuit which can operates stably during a period from a time when the DLL circuit is started, namely, from an unlock state (the state that the phase difference between the external clock signal and the internal clock signal does not fall within a predetermined range) to the lock state (the state that the phase difference between the external clock signal and the internal clock signal falls within the predetermined range).
Still another object of the present invention is to provide a semiconductor device such as a synchronous DRAM which contains the above DLL circuit.
Yet still another object of the present invention is to provide a delay control method in the above DLL circuit.
In an aspect of the present invention, a DLL (delay locked loop) circuit includes a signal propagation system and a delay control system. The signal propagation system includes a delay circuit which delays a reference clock signal based on a delay control signal to generate a delayed clock signal. The delay control system includes a sampling circuit, a phase comparing circuit and a delay control circuit. The sampling circuit outputs a first clock signal having a pulse corresponding to one of n (n is an integer more than 1) pulses of the delayed clock signal. The phase comparing circuit compares the first clock signal as a first comparison input signal and the reference clock signal as a second comparison input signal in phase to output a phase difference.
The delay control circuit generates the delay control signal based on the phase difference from the phase comparing circuit to output to the delay circuit of the signal propagation system.
The signal propagation system may further include an input circuit which inputs an external clock signal as the reference clock signal to output to the delay circuit. In this case, the delay control system further includes an input dummy circuit which delays the first clock signal from the sampling circuit by a delay quantity corresponding to that of the input circuit to output to the phase comparing circuit as the first comparison Input signal.
Also, the signal propagation system may further include an output circuit which inputs the delayed clock signal from the delay circuit to output the delayed clock signal as an internal clock signal. In this case, the delay control system further includes an output dummy circuit which delays the first clock signal from the sampling circuit by a delay quantity corresponding to that of the output circuit to output to the phase comparing circuit as the first comparison input signal.
Instead, the signal propagation system may further include an input circuit which inputs an external clock signal to output to the delay circuit as the reference clock signal, and an output circuit which inputs the delayed clock signal from the delay circuit to output as the internal clock signal. In this case, the delay control system further includes a dummy circuit which delays the first clock signal from the sampling circuit by a delay quantity corresponding to a summation of a delay quantity of the input circuit and a delay quantity of the output circuit to output to the phase comparing circuit as the first comparison input signal.
Also, the phase comparing circuit may output the phase difference between the first comparison input signal and the second comparison input signal as with respect to a phase of the first comparison input signal. In this case, the phase comparing circuit may output as the phase difference, lead or delay of a phase in a rising edge of the second comparison input signal with respect to a phase in a rising edge of the first comparison input signal.
Also, the sampling circuit may include a frequency divider and a selection output circuit. The frequency divider divides a frequency of the delayed clock signal into 1/n to generate a division signal. The selection output circuit selectively outputs a pulse corresponding to each of the pulses of the delayed clock signal based on the division signal.
In this case, the selection output circuit may include a clocked inverter connected with an output of the frequency divider to invert the delayed clock signal, and an N-channel transistor having a gate terminal connected with an output of the frequency divider, a drain terminal connected with an output of the clocked inverter and a source terminal grounded.
Also, the frequency divider may include a flip-flop which divides the frequency of the delayed clock signal into xc2xd, and an inverter which inverts an output of the flip-flop. Instead, the frequency divider may include a flip-flop which divides the frequency of the delayed clock signal into xc2xd, and a NOR circuit which outputs a NOR operation result of an output of the flip-flop and a sampling control signal. In this case, the sampling control signal is in an L level normally and is in a H level in an active state, and indicates whether the delay signal should be outputted in synchronism with the division signal or continuously.
Also, the DLL circuit may further include a frequency divider which divides a frequency of the reference clock signal into 1/m (m is a divisor of n except for 1) and inverts and supplies to the phase comparing circuit as the second comparison input signal.
In another aspect of the present invention, a delay control method is attained by (a) generating a reference clock signal from an external clock signal supplied via an input buffer; by (b) delaying the reference clock signal based on a delay control signal to generate a delayed clock signal; by (c) outputting the delayed clock signal via an output buffer; by (d) sampling a pulse corresponding to one of n (n is an integer more than 1) pulses of the delayed clock signal to output a first clock signal; by (e) delaying the first clock signal by a summation of a delay quantity of the input buffer and a delay quantity of the output buffer to generate a second clock signal; by (f) comparing the second clock signal as a first comparison input signal and the reference clock signal as a second comparison input signal in phase to output a phase difference; and by (g) generating the delay control signal based on the phase difference.
Also, the (d) sampling step may be attained by dividing a frequency of the delayed clock signal into 1/n to generate a division signal; and by selectively outputting a pulse corresponding to each of the pulses of the delayed clock signal based on the division signal.
Also, the (f) comparing step may be attained by outputting the phase difference between the first comparison input signal and the second comparison input signal as with respect to a phase of the first comparison input signal.
Instead, the (f) comparing step may be attained by outputting lead or delay of a phase of a rising edge of the second comparison input signal as the phase difference with respect to a phase of a rising edge of the first comparison input signal.
Also, the delay control method may further include: dividing a frequency of the reference clock signal into 1/m (m is a divisor of n except for 1) to generate a frequency-divided clock signal; and inverting the frequency-divided clock signal to output as the second comparison input signal.